Consumers and businesses increasingly demand greater performance and functionality from electronics products while simultaneously desiring decreased size, cost and power consumption. Therefore, OEMs that design products such as mobile phones, digital TVs, home networking products, video game consoles, portable media players and office automation equipment are choosing to integrate as many functions as practicable into a single SoC in order to achieve size, cost and power consumption goals for their next-generation products.

According to Semico Research, the interconnect segment of the semiconductor intellectual property market is projected to have a five-year compound annual revenue growth rate of 31% from 2006 to 2010; this represents the highest such rate of any segment of the market, and is nearly two times the growth rate of the total market. In addition, Gartner estimated that 2006 worldwide SoC revenue was $56.3 billion, accounting for 21.4% of the total semiconductor market, and in 2011 will reach $88.4 billion, or 26.2% of the total semiconductor market.

The traditional design approach for SoCs is based upon single processor-based computer systems, where the interconnect is a simple bus structure defined by the system processor. The traditional approach encounters interconnect design problems in SoCs with numerous IP cores that are each optimized to perform different application-specific functions. These problems include limiting the SoC’s achievable performance and requiring significant external logic to bridge each different IP core to a bus that is based on a single processor’s clock frequency, data path width and interface protocol. Accordingly, the number of potential design failures due to IP core interoperability issues is significant.

Introduced in 2006, SonicsLX is the Company’s newest interconnect product. SonicsLX contains a high-performance advanced fabric and a limited set of data flow services and is designed for SoCs that employ multiple complex IP cores. SonicsLX targets Value SoC applications such as wireless baseband, digital cameras, digital set top box and MP3 players. SonicsLX offers a direct upgrade path to SonicsMX.

Introduced in 2004, SonicsMX is the Company’s flagship interconnect product. SonicsMX contains a high-performance advanced fabric and a comprehensive set of data flow services and is designed for SoCs that employ heterogeneous multiprocessor architectures. SonicsMX targets complex SoC applications such as application processors, high-definition video applications, office automation products and automotive electronics. SonicsMX offers the highest performance, highest scalability and largest feature set of the Company’s products.

Introduced in 2002, Sonics3220 is the Company’s peripheral interconnect product and targets the growing number of lower complexity and performance peripheral IP cores in SoC applications with a wide variety of input/output ports such as wireless and consumer application specific standard products. The Company’s customers typically use Sonics3220 together with one of its other interconnect products.

Introduced in 1999, SiliconBackplane is the Company’s first generation interconnect product. This product is currently in volume production in networking, wireless LAN, digital television and gaming semiconductor devices.

SonicsStudio is a software platform that provides the integration environment for the Company’s SMART Interconnect solutions. SonicsStudio delivers a graphical user interface for integrating IP cores into a model of the SoC, configuring advanced fabric features and data flow services and generating and verifying the fully connected and configured SMART Interconnect. The Company’s SonicsStudio conforms to industry standard data formats for use in various simulation environments and analyzes the results of those simulations to measure performance.

The Company’s MemMax Memory Scheduler is an IP core that maximizes the efficiency of an SoC’s access to external DRAM resources while ensuring QoS. MemMax leverages a multi-threaded non-blocking socket interface to one of the Company’s interconnects and also interfaces to a DRAM controller.

Cost of revenue was $241,000 and $177,000 for the three months ended June 30, 2006 and 2007, respectively, a decrease of $64,000, or 26.6%.

Research and development expenses were $1.2 million and $1.5 million for the three months ended June 30, 2006 and 2007, respectively, an increase of $327,000, or 27.7%.