The digital integrated circuits used in most electronic systems can be broadly categorized into three classifications: processors, which are used for control and computing tasks; memory devices, which are used for storing program instructions and data; and logic devices, either fixed or programmable, which are used for managing the interchange and manipulation of digital signals within a system; logic devices contain interconnected groupings of simple logical “and” and “or” and other logic functions, known as gates, to create more complex functions, and these complex combinations of individual gates are required to implement specialized logic functions required for a system.

Manufacturers of electronic systems are increasingly attracted to solutions that can reduce product development time and cost and shorten time-to-market. The typical ASIC design time to first silicon is about 18 months, while the design time for a corresponding FPGA is about 12 months. The shorter development cycle of programmable logic is a direct result of the development process steps the designer must go through to complete a design. The development process for an ASIC involves the complex task of using basic logic elements such as “and” and “or” gates to construct complex functions and algorithms. These blocks of logic are then expressed as transistor circuits that are physically implemented in a form that can be built as a silicon chip. The FPGA development process typically involves the same initial steps. However, instead of reducing the logic blocks to physical circuits, the logic functions are programmed into pre-designed blocks of logic, thus reducing the time-to-market for FPGAs as compared to ASICs. The FPGA vendors offer a range of products that contain differing numbers of blocks of logic targeting a range of different applications. The number of new programmable logic designs initiated by customers of ASIC and FPGA vendors indicates the industry’s growing interest in programmable logic devices. According to publicly-available information from Gartner/Dataquest, the number of new ASIC design starts began to decline from approximately 10,000 new designs in 1998 to less than 4,000 in 2004. During the same period, the capabilities of FPGAs as measured by the number of logic cells was being increased to the point that high performance FPGAs were suitable for the implementation of much larger portions of a system design, thus representing a viable alternative to ASICs.

The Company’s FPOA architecture simplifies the silicon design process. ASIC and FPGA devices require the designer to perform the complex task of implementing algorithms using millions of individual logic gates. FPOA designers implement these algorithms by programming a few hundred interconnected silicon objects, reducing design costs and improving overall system performance and time-to-market.

The Company is developing a library of different silicon object types that can be inserted in the array in any pattern. The Company’s object types include an arithmetic logic unit, a truth table, a register file and a multiply/accumulate unit. The Company is designing additional object types, including content addressable memory and cyclical redundancy check. Each of these object types can be programmed to perform a number of different functions, thus enabling this relatively small number of object types to satisfy a wide range of applications. Each of the object types shares a common interface to the interconnect system.

The Company offers a customer development kit consisting of an FPOA chip, a prototype board and software design tools. This kit enables the customers to create an FPOA design, simulate the functionality and performance of the design, program the FPOA and test the chip using a standard personal computer. The Company currently has a limited supply of its first FPOA chips available for sale.

The Company is developing, and plans to provide its customers access to, a library of application programs for its FPOA. To date, the Company has implemented and offer eight different application algorithms, including fast fourier transforms, digital filters and digital encoders. These applications are fully tested and documented, allowing the customers to use them as is or to easily modify them for their specific needs.

For the six months ended June 30, 2005, research and development expenses increased 119% to $4.6 million compared to $2.2 million for the six months ended June 30, 2004.

For the six months ended June 30, 2005, selling, general and administrative expenses increased $635.0 thousand or 35% to $2.5 million compared to $1.8 million for the six months ended June 30, 2004.

For the six months ended June 30, 2005, other expenses net were $469.0 thousand compared with other income of $33.0 thousand for the six months ended June 30, 2004.